1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device suitably used for a large capacity memory.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing the basic construction of a conventional typical semiconductor memory device. One column of the memory cell array of the conventional typical semiconductor memory device (which is referred to as a semiconductor memory hereinafter) is shown in FIG. 1. The semiconductor memory has a plurality of memory cells 2. Each of the memory cells 2 is connected in a branch form to a corresponding one of a plurality of word lines 104 and a corresponding one of a plurality of bit lines 112. The bit line 112 has not only a memory cell selecting function which is attained in cooperation with the word line, but also has a function of providing a data transmission path to the selected memory cell. Generally, the plurality of word lines 104 are arranged in parallel to extend in one direction and one ends thereof are connected to a decoder (not shown). Further, the plurality of bit lines 112 are arranged in a direction intersecting with the word lines 104 at a preset angle, for example, 90 degrees and one ends thereof are connected to a read/write circuit 26e. At the time of read/write operation, a word line and a bit line are selected by the row decoder and column decoder according to an address signal for a memory cell 2 to be accessed. Then, only a specified selected memory cell 2 that is connected to the selected single word line 104 and single bit line 112 can be accessed. The read/write circuit 26e to which one end of the bit line associated with the selected memory cell 2 is connected effects the read/write operation for the selected memory cell 2 via the bit line 112 serving as the data transmission path.
FIG. 2 is a circuit diagram showing the basic construction of another conventional semiconductor memory. Each bit line is constructed by a complementary signal line pair. Each memory cell 3 is connected to corresponding bit lines which are constructed by a pair of signal lines 113a, 113b. Transfer gates 28a, 28b are serially connected between a read/write circuit 26f and the respective bit lines 113a, 113b. Reference numerals 36a, 36b denote data lines. The read/write operation of the memory in FIG. 2 is the same as that of FIG. 1. In FIGS. 1 and 2, power sources and peripheral circuits such as a row decoder are not shown for simplifying the drawing.
As the memory capacity of the above semiconductor memory tends to be largely increased, problems clearly arise accordingly to its large capacity. Generally, breaking of wires of the semiconductor memory occurs with a certain probability. As the total length of the wire is increased with an increase in the memory capacity, the probability of occurrence of one or more breakings of the wires in one chip becomes high. Particularly, it becomes extremely difficult to manufacture memory cell arrays which do not contain breaking of bit and/or word wires at all. For example, in FIG. 1, when breaking of wire occurs on the half way of the bit line 112 which straightly extends from the read/write circuit 26e, memory cells which lie on the opposite side with respect to the breaking portion of the bit line as viewed from the read/write circuit 26e cannot be accessed. That is, defective bits occur. It should be noted that even if the defective bits is only one bit, the memory chip cannot be used at all. When the breaking of wire occurs in the manufacturing process, it becomes a main factor of low manufacturing yield. This is a serious problem for manufacturing the semiconductor memory device.
FIG. 3 is a schematic block diagram showing the construction of a semiconductor memory having a column redundant circuit additionally provided. As a means for protecting the memory chip from becoming a defective product caused by occurrence of defective bits, an additional redundant circuit is used. FIG. 3 is a conceptional diagram of a column redundant circuit used as an example of a redundant circuit. When a column redundant circuit corresponding to one column of the memory cell array is provided, the whole portion of a column of the memory array 1i to which the defective bit belongs is replaced with a spare column 56 by means of a switching circuit 58 if a defective bit is detected in the memory test. In general, a plurality of row redundant circuits and/or a plurality of column redundant circuits are prepared. However, the number of rows or columns which can be backed up by the redundant circuits is limited. Further, there are provided various types of memories in which redundant circuits cannot be easily formed because each cell thereof is not equivalent as in a cache memory or it has a limitation in the layout. Therefore, use of the redundant circuit is not sufficient to protect a memory chip from becoming a defective product caused by occurrence of a defective bit in the present state. Further, if breaking of wire due to deterioration with time such as electromigration occurs in use, an impact is given to the whole system and the reliability of the elements is degraded. It also causes a serious problem. However, in the present state, the redundant circuit has no practical effect for breaking of wire in the semiconductor memory in use and no effective recovery means can be provided. Since the memory chip is manufactured through a large number of steps, it is desired from the viewpoint of manufacturing yield to develop more effective means for preventing occurrence of defective chips even when breaking of wire has occurred. Besides, from the viewpoint of reliability, it is desired to develop means which can be effectively used not only in the manufacturing process but also at the time of use.